MT9075BL

Single Chip Transceiver, QFP, 20 dB LIU dynamic range, -0.3 to 7 V Supply Voltage, 30 mA Current

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Price:: US $0.10~100.00 / piece [Get Latest Price]

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	US $0.10~100.00

PartNumber:: MT9075BL

Brand:: Mitel Networks Corporation - Mitel | Pack: QFP | D/C: 10+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2011-08-09

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Part Number:MT9075BL
US $0.10 - 100.00
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Product Summary

The MT9075BL is a single chip device which integrates an advanced PCM 30 framer with a Line Interface Unit (LIU). The framer interfaces to a 2.048 Mbit/s backplane and provides selectable rate data link access with optional HDLC controllers for Sa bits and channel 16. The LIU interfaces the framer functions to the PCM 30 transformer-isolated four wire line. The MT9075BL meets or supports the latest ITU-T Recommendations including G.703, G.704, G.706, G.732, G.775, G.796, G.823 for PCM 30, and I.431 for ISDN primary rate. It also meets or supports ETSI ETS 300 011, ETS 300 166 and ETS 300 233 as well as BS 6450.

Parametrics

MT9075BL absolute maximum ratings: (1)Supply Voltage VDD: -0.3 to 7 V; (2)Voltage at Digital Inputs VI: -0.3 to VDD + 0.3 V; (3)Current at Digital Inputs: 30 mA; (4)Voltage at Digital Outputs VO: -0.3 to VDD + 0.3 V; (5)Current at Digital Outputs IO: 30 mA; (6)Storage Temperature TST: -55 to 125 ℃.

Features

MT9075BL features: (1)Combined PCM 30 framer, Line Interface Unit (LIU) and link controllers in a 68 pin PLCC or 100 pin MQFP package; (2)Selectable bit rate data link access with optional Sa bits HDLC controller (HDLC0) and channel 16 HDLC controller (HDLC1); (3)LIU dynamic range of 20 dB; (4)Enhanced performance monitoring and programmable error insertion functions; (5)Low jitter DPLL for clock generation; (6)Operating under synchronized or free run mode; (7)Two-frame receive elastic buffer with controlled slip direction indication; (8)Selectable transmit or receive jitter attenuator; (9)Intel or Motorola non-multiplexed parallel microprocessor interface; (10)CRC-4 updating algorithm for intermediate path points of a message-based data link application; (11)ST-BUS/GCI 2.048 Mbit/s backplane bus for both data and signalling.